The headline number is 200 gigabits per second on a single wavelength. The more interesting number is 11: the number of equalizer taps needed at the receiver to get there. State-of-the-art datacenter transceivers routinely throw nearly 100-tap equalizers at the same problem, and the drivers and DSP that do that work consume watts. A team from the Institute of Science Tokyo, Yokohama National University, AIST, and the Photonics Electronics Technology Research Association (PETRA) has now shown a silicon modulator that reaches 200 Gb/s per lane with a fraction of that electronic effort — by moving the equalization out of the DSP and into the modulator itself.
The paper, published October 22 in Nature Communications, is titled “Reduced-DSP 200G/λ low-voltage slow-light silicon modulator enabled by built-in EO equalizer.” Its lead author is Keisuke Kawahara, and the senior author is Toshihiko Baba of Yokohama National University. The device is a silicon photonic-crystal waveguide modulator in which light is deliberately slowed down, and a built-in electro-optic equalizer flattens the frequency response that slow light would otherwise degrade. The result is a modulator 320 micrometers long, driven at 1.5 volts peak-to-peak, that transmits 200 Gb/s PAM4 with an 11-tap receiver equalizer — and 180 Gb/s PAM4 with no DSP at all.
The bandwidth-efficiency trap
A silicon Mach-Zehnder modulator works by changing the refractive index of silicon through the free-carrier plasma dispersion effect: a voltage applied to a p-n junction changes the carrier density, which changes the index, which changes the phase of light in one arm of the interferometer. The trouble is that the effect is weak. Carrier-depletion phase shifters typically have a voltage-length product, VπL, of 2 to 5 V·cm. That is why conventional silicon modulators are millimeters long and need high-swing drivers: a weak effect stretched over a long device, driven hard, to get enough phase shift.
Long electrodes bring their own penalty. RF propagation loss along a millimeter-scale electrode, combined with the RC time constant of the junction and the mismatch between the speed of the electrical signal and the optical wave, caps the electro-optic bandwidth below about 50 GHz. To push past 100 Gb/s per lane anyway, transceiver designers compensate with electronics: standalone high-swing drivers and complex DSP with nearly 100-tap equalizers. Those components consume watt-level power, and in a datacenter where thousands of transceivers run continuously, that power is a large share of the link budget and a growing share of the facility’s power.
Slow light: more interaction per micrometer
A photonic-crystal waveguide is a silicon waveguide patterned with a periodic array of tiny holes — in this device, a triangular lattice with a 404-nanometer period and 230-nanometer holes. The periodicity creates a band structure for light, and near the band edge the group velocity of light drops sharply. The light lingers. Its group index, the factor by which it is slowed relative to vacuum, runs from 20 to 70 in this device, compared with about 4.3 for an ordinary silicon ridge waveguide.
Slow light is a lever on modulation efficiency. Light that spends more time in the phase shifter interacts more strongly with the index change, so a given voltage produces a larger phase shift. The measured VπL of this device ranges from 0.51 to 0.16 V·cm across the group-index range — roughly an order of magnitude better than a conventional silicon modulator. That is what allows the whole device, main tap and equalizer sections included, to fit in 320 micrometers: a 180-micrometer main tap and a 140-micrometer equalizer section, with a total footprint including electrodes of just 0.4 square millimeters. Against conventional modulators of 2 to 4 millimeters, that is roughly a tenfold shrink.
But slow light has a catch. The same physics that slows the light also makes the device electrically sluggish: the large electrical resistance of the slow-light structure limits high-frequency bandwidth more severely than in a conventional modulator. Earlier slow-light modulators hit this wall at a 3-dB bandwidth below 40 GHz and 64 Gb/s on-off keying — the efficiency was there, the speed was not. Grating-based slow-light modulators have reached 200 Gbaud PAM4, but with a Vπ of several tens of volts and neural-network DSP doing the heavy lifting. Speed bought with voltage and DSP is exactly the bargain this work refuses.
The equalizer, built into the optics
The core idea of the new paper is to stop treating equalization as something electronics does after the fact, and instead build a finite-impulse-response filter into the modulator’s optical structure. The phase shifter is divided into segments, with coplanar transmission lines between them. An optical delay line and an optical crossing sit in front of the last segment. The delay line shifts the timing of the last segment’s contribution, and the crossing inverts its modulation sign. The result is a two-tap feed-forward equalizer implemented in light: a main tap with amplitude N−1 and an equalizer tap of amplitude −1, arriving slightly earlier.
In frequency terms, the equalizer has a high-pass response that compensates the device’s intrinsic low-pass roll-off. The two design knobs are independent: the segment count N sets the equalization strength, and the tap delay sets the peak frequency. With N = 4 and a tap delay of 6.8 picoseconds, the response is at its flattest. The N = 3 device’s 3-dB bandwidth rose from 35 GHz to 80 GHz with the equalizer engaged; the N = 4 device’s rose from 23 GHz to 55 GHz, with a flatter response. Across the device’s operating wavelengths, bandwidth above 50 GHz was observed at almost all wavelengths — enough to satisfy the Nyquist criterion for 200 Gb/s PAM4, which runs at 100 Gbaud.
There is a subtlety that makes the equalizer practical rather than merely clever. In a long modulator, frequency-dependent RF loss distorts the equalizer response, which is one reason earlier electro-optic equalizers struggled with multilevel modulation. Here the device is so short that RF propagation loss is suppressed, and the segmented structure pushes the roll-off from intra-segment phase mismatch beyond 100 GHz. The equalizer therefore only has to flatten a gentle roll-off, needing a small peak gain. The shortness of the device and the quality of the equalizer reinforce each other.
The measurements, in full
The headline experiment used the N = 4 device, chosen for its flatter response. The drive conditions are worth stating precisely, because low voltage is half the claim. The p-n junction was biased at −2.5 V. For on-off keying, clear eye openings were maintained at 100 Gb/s and 112 Gb/s down to drive swings of 0.8 V and 0.7 V peak-to-peak, respectively. For PAM4, clear eyes were observed from 140 to 200 Gb/s at drive swings of 2.0 down to 1.5 V peak-to-peak.
The DSP story needs to be told in two parts, because the paper’s title says “reduced-DSP,” not “DSP-free,” and the distinction matters. With no DSP at all, the equalizer alone delivered 180 Gb/s PAM4, with the transmitter-and-dispersion eye closure penalty (TDECQ) held at or below 2.2 dB up to 180 Gb/s. At 200 Gb/s without DSP, the TDECQ rose to 4.9 dB — an eye was still visible, but outside the roughly 3–4 dB range the authors treat as the typical acceptable limit. Adding a low-complexity 11-tap symbol-spaced feed-forward equalizer at the receiver brought 200 Gb/s PAM4 to a TDECQ of 1.5 dB, with a modulator bit energy of 63 femtojoules per bit. The same 11-tap equalizer took on-off keying to 140 Gb/s at just 0.6 V drive and 26 fJ/bit.
Those energy figures deserve context. The paper cites prior slow-light modulators below 59 fJ/bit for the modulator alone, and 0.78 pJ/bit with a co-packaged driver. Conventional silicon modulators at the same data rate expend, in the coverage of this work, several thousand femtojoules per bit. The claim is not that 63 fJ/bit is a system-level figure — it is the modulator’s drive energy, not the full transceiver’s — but the direction and the size of the gap are the point. A modulator that needs 1.5 V instead of 5 V can be driven by advanced CMOS rather than a standalone high-swing driver, and the paper notes that the 1.5 V swing and 100 Gbaud symbol rate are consistent with demonstrated 5-nanometer FinFET drivers. That is the path by which a device result becomes a power result: not just a better modulator, but a modulator that lets the surrounding electronics get simpler and cheaper.
Fabrication is the other half of the practicality claim. The device was built in a 300-millimeter silicon-on-insulator foundry process at AIST, using argon-fluoride immersion lithography, with every structural dimension above the roughly 150-nanometer minimum feature size of standard silicon photonics processes. No exotic material, no wafer bonding, no specialized step of the kind thin-film lithium niobate requires. If this device ever reaches manufacturing, it would ride the existing silicon photonics line.
What it is not — yet
The honest reading of this paper requires its caveats, and the authors supply them. The largest is insertion loss: 11.7 to 15.5 dB. That is high for a link component. In the measurement setup it was compensated by an erbium-doped fiber amplifier, which is a laboratory convenience, not a datacenter component. For co-packaged optics, the authors state plainly, this loss needs to be reduced, and they express confidence that design optimization can do it. Confidence is not a demonstration. Until loss comes down, the power saved in drivers and DSP could be spent again in optical amplification, and the link budget math has to be redone.
The second caveat is spectral width. The measured operating window of the present device is 6 nanometers. That is enough for a single wavelength, and the authors sketch a route to 16- to 32-channel wavelength-division multiplexing — either by integrating multiple modulators tuned to different windows, or by using lattice-shifted photonic-crystal waveguides that have demonstrated 35-nanometer bandwidths — projecting 3.2 to 6.4 Tb/s aggregate. But that is a projection, explicitly framed as such, not a multiplexed demonstration. A 200G lane is the on-ramp to 1.6-terabit and 3.2-terabit transceivers only if the lanes can be multiplied, and multiplication is still on the to-do list.
The third caveat is the nature of the measurement itself. These are transmitter characterization results: eye diagrams and TDECQ against a soft-decision forward-error-correction threshold of 2 × 10⁻² bit error rate, with waveform averaging to suppress amplifier noise. The authors note that real transceiver links will ultimately require bit-error-rate-based measurements. There is no receiver, no fiber transmission, no packaged device, and no reliability data here. This is a modulator result, not a transceiver result, and it should not be reported as anything more.
None of this diminishes the result. It locates it. What is unusual here is a device that is simultaneously fast, low-voltage, compact, and CMOS-fabricable, with its main weakness stated in the open and a plausible path to fixing it.
Why 200G lanes are the hinge
The industry significance is about arithmetic. A 1.6-terabit transceiver needs eight lanes at 200 Gb/s; a 3.2-terabit transceiver needs sixteen. Today’s 100G lanes, multiplied, mean more lasers, more modulators, more fibers, and more DSP power per terabit. Doubling the per-lane rate halves the lane count, and if each lane also needs less DSP and a smaller driver, the savings compound. That is why the per-lane number matters more than the aggregate: it determines how many parallel paths a future transceiver must build, power, and package.
It is also why the “reduced” in reduced-DSP matters as much as the “200G.” As symbol rates rise, equalizer complexity and power rise with them, and at some point the electronics cost more than the optics they are rescuing. A modulator that carries its own equalization — even with an 11-tap assist at the receiver — points at a different division of labor between photonics and electronics, one in which the device does more and the DSP does less.
The signals to watch: insertion loss coming down without giving back bandwidth or voltage; a multiplexed demonstration of several of these modulators on one chip at different wavelengths; and a packaged link — CMOS driver, modulator, fiber, receiver — measured by bit error rate rather than eye quality. Any one of those would move this from a device paper to a transceiver story.
For now, the fair summary is this: a slow-light modulator that was supposed to be too slow for 200G lanes got there by equalizing itself, at a voltage a CMOS driver can supply, in a footprint ten times smaller than the incumbent, on a standard silicon photonics line. The loss is too high and the window too narrow for deployment today. But the trade-off that has defined silicon modulators — efficiency or bandwidth, not both — now has a counterexample, and counterexamples have a way of rearranging roadmaps.
Sources and further reading
Kawahara, K., Tsuchizawa, T., Yamamoto, N., et al. “Reduced-DSP 200G/λ low-voltage slow-light silicon modulator enabled by built-in EO equalizer.” Nature Communications 17, 10446 (2026). DOI: 10.1038/s41467-026-78128-1. All device figures in this article — dimensions, voltages, bandwidths, energies, insertion loss, and spectral window — are from this paper. Coverage in SemiEngineering (October 25, 2026) and the Yokohama National University announcement carried by Tech Xplore and Asia Research News (October 22, 2026) provided the publication timeline and institutional context. Projections about multiplexed capacity (3.2–6.4 Tb/s) and future loss reduction are the authors’ own, as stated in the paper’s Discussion, and are reported here as projections, not results.