On October 1, ficonTEC Service GmbH and Hermes Testing Solutions Inc. (HTSI) announced a strategic cooperation to industrialize ficonTEC’s double-sided electro-optical wafer-level test platform for co-packaged optics (CPO) manufacturing in Taiwan. The announcement, issued from Achim, Germany and Hsinchu, Taiwan, surfaced in aggregator coverage in early November — a month after the fact, which is itself part of the story. This is not breaking news, and it is not a shipment. It is a cooperation agreement about manufacturing capacity: a German photonics test equipment maker pairing its wafer-test architecture with a Taiwanese test-services company that can build, install, and service it locally. In the CPO story, the unglamorous question of who tests the wafers — and where, and at what throughput — decides whether the devices ever reach volume.
That framing matters because the temptation with any CPO announcement is to read it as a production milestone. This one is not. No customer is named, no system has been delivered under the cooperation, no volume is stated, and no qualification timeline is given. What the two companies have actually agreed to do is narrower and, in its own way, more consequential than a single order: to take a test platform that exists and make it manufacturable, deliverable, and supportable at scale in Taiwan. If CPO’s bottleneck is test capacity, then industrializing the test step is the work that has to happen before any volume announcement can be believed.
What was actually announced
Precision first. ficonTEC Service GmbH, described in the release as a global provider of automated photonic assembly and test solutions, and HTSI, a Taiwan-based provider of semiconductor testing solutions, announced a strategic cooperation to support the expanding CPO ecosystem in Taiwan. The initial focus, stated explicitly, is “the industrialization and scalable deployment” of ficonTEC’s double-sided electro-optical wafer-level test platform, referred to within the CPO insertion flow as INS-2, for advanced silicon photonics wafer testing.
The cooperation combines two things that neither company has alone. From ficonTEC: experience in silicon photonics and CPO test automation, embodied in the INS-2 platform. From HTSI: established semiconductor equipment manufacturing, engineering, and local service capabilities, plus more than 20 years of semiconductor testing expertise. The stated output is localized equipment delivery, responsive local engineering support, and a scalable manufacturing path as CPO test demand increases.
The companies also say the cooperation extends beyond equipment delivery. They plan a collaborative engineering framework covering rapid design reviews, local system integration, installation, qualification, service, and continuous improvement of the INS-2 platform, supporting evaluation of the manufacturing metrics that matter once CPO moves into volume production: units per hour (UPH), equipment availability, and process stability. Note the tense throughout: “plan,” “intend,” “aim.” This is a framework being established, not a production line being reported.
The executive quotes carry the same message in plainer language. “The transition of CPO from technology development to industrial manufacturing requires more than innovative devices — it requires manufacturing capacity,” said Stefano Concezzi, CMO and Corporate Vice President of ficonTEC, adding that the goal is to “shorten delivery times, provide strong local engineering and service, and continuously improve the productivity and yield of the platform as customers move toward volume production.” Steven Wang, President of HTSI, said Taiwan “plays a critical role in the global semiconductor and AI supply chain” and that the companies “intend to provide customers with a highly responsive local solution from system deployment through production support and continuous improvement.”
Read those quotes for what they promise and what they do not. Shorter delivery times, local service, continuous improvement — plausible benefits of localization, but none is a delivered result. The cooperation is the mechanism; results, if they come, will be visible in deployments.
Why double-sided test is the hard part
To understand why a test-platform cooperation deserves this much attention, recall what CPO does to the wafer. In a conventional pluggable transceiver, the photonic integrated circuit (PIC) is packaged, fiber-attached, and tested as a finished module. In CPO, the optical engine sits on the switch package substrate itself, and in the most advanced flows the photonic and electronic dies are hybrid-bonded — joined at wafer level before dicing. A defect found after bonding or packaging is no longer a scrapped chip; it is a scrapped assembly that may include a switch ASIC worth far more than the optical die. The logic of wafer-level test for CPO is therefore simple: find the bad dies before they are bonded into something expensive. Known-good-die testing, familiar in electronics, becomes a survival requirement in photonics, where a single bad optical channel can condemn a multi-thousand-dollar package.
The catch is that testing a silicon photonics wafer is not like testing an electronics wafer. A conventional prober touches electrical pads and measures electrical responses. A photonics wafer must be tested electrically and optically at the same time: the device takes electrical signals in and produces light out, or the reverse, and its performance — insertion loss, responsivity, modulation quality — can only be known by coupling light into and out of it while it is still on the wafer. The test system must align fibers to couplers with sub-micron precision, hold that alignment while the wafer is probed electrically, and do it fast enough that testing does not bottleneck the fab.
This is where the double-sided architecture comes in. The INS-2 platform is a 300 mm double-sided electro-optical wafer-level test architecture: electrical probing from the top of the wafer, precision optical access from below. The system includes a customized slotted wafer chuck — the slot is what makes optical access from below possible — precision wafer positioning, a six-axis optical alignment engine, automated wafer handling, vision, and probe inspection and cleaning, all described as designed for high-throughput manufacturing environments.
The double-sided approach answers a real physical constraint. On a photonics wafer, the top surface is crowded: electrical pads, probe needles, and prober hardware all compete for the space optical coupling would want. Approaching the optics from below, through a slotted chuck, separates the two access problems. The six-axis alignment engine matters because optical coupling is unforgiving — a misalignment of a fraction of a micron can cost decibels of coupling loss, and a test that cannot distinguish a bad device from a bad alignment is worse than no test at all. Automated handling, vision, and probe inspection and cleaning are the infrastructure of throughput: wafer loading, alignment-mark finding, and probe maintenance determine units per hour, the metric the cooperation names.
One further design choice shapes the business model, not just the engineering. The platform is ATE-agnostic, designed to integrate with industry-standard semiconductor automated test equipment (ATE) so customers can deploy the optical test capability within their existing ATE infrastructure rather than buying into a closed architecture. That matters because the ATE installed base is one of the most entrenched pieces of semiconductor capital equipment: a test cell that docks with existing ATE can be adopted by a foundry or OSAT without replacing its test floor. ficonTEC has walked this road before, pairing its optical alignment, probing, and wafer-handling technology with Teradyne’s UltraFLEXplus ATE in a double-sided wafer probe test cell for silicon photonics. The HTSI cooperation extends the same logic from a product pairing to a manufacturing and service footprint.
Why Taiwan, and why a local partner
The geography of this announcement is not incidental. Taiwan is where the CPO supply chain concentrates: the foundries that make the silicon photonics wafers, the OSATs that package them, and the advanced-packaging lines that assemble CPO devices all sit within a few hours of Hsinchu. A platform built in Germany and shipped to Taiwan carries delivery lead time and service latency a locally built and serviced platform does not. The release says so directly: the cooperation is meant to provide “localized equipment delivery” and “responsive local engineering support.” For a customer qualifying a test cell on a production ramp, the difference between a field-service engineer a flight away and one an hour away is the difference between a day of downtime and a week of it.
HTSI’s role, as described, is exactly the local half of that equation: semiconductor equipment manufacturing, engineering, and service capabilities in Taiwan, built over more than two decades in semiconductor testing. What the release does not specify is the division of manufacturing labor — which subsystems HTSI will build versus integrate, whether INS-2 systems will be assembled in Hsinchu from ficonTEC modules or manufactured more fully in Taiwan, or what the first deliverable under the cooperation will be. Those specifics are the difference between a cooperation and a supply chain, and they are not yet on the record.
There is also a broader ecosystem read, which the release itself invites. The cooperation is described as part of ficonTEC’s wider effort with Taiwan and North American semiconductor, photonics, test, and manufacturing companies to accelerate the industrialization of silicon photonics. That is a fair description of how CPO actually gets built — no single company owns the stack. The test step is genuinely ecosystem-shaped: it sits between the foundry and the OSAT, touches the ATE vendor’s platform, and serves whoever owns the wafer at the moment of test. A cooperation structured as a joint engineering framework, rather than a simple distribution deal, fits that shape.
The timing within the CPO calendar is worth noting, carefully. This desk covered Tower and Innolight’s first near-package optics device entering early production on November 3, and the Marvell–Lumentum acquisition agreement the day before that. Test capacity is the shared constraint behind both arcs: whether the device is a near-package engine on a board or a co-packaged engine on a switch substrate, its photonic dies must be tested at wafer level before they are committed to an expensive assembly. An industrialized double-sided test platform in Taiwan serves both architectures, not just one.
What is undisclosed, and why it matters
An honest accounting of what this announcement does not contain is part of the story. No customer is named — no foundry, OSAT, or device maker is identified as a buyer or evaluator of INS-2 under the cooperation. No volume, delivery schedule, or revenue figure is given. No qualification timeline is stated: no date by which an INS-2 system is expected to be qualified in a customer fab, and no statement that any system has been qualified yet. No performance figure for the platform is disclosed — no units-per-hour number, no alignment accuracy specification, no throughput claim beyond the general description of the architecture as designed for high-throughput environments. No price, no order, and no exclusivity term is mentioned.
Each omission has a plausible innocent explanation. Cooperation agreements routinely precede customer disclosures; qualification timelines are customer-confidential; throughput figures depend on the device under test and are meaningless without it. But the pattern of omissions sets the limit of what can responsibly be claimed here. This article asserts no customer, no deployment, no qualification, and no throughput figure for INS-2 in Taiwan, because none is on the record. Any coverage that attaches a customer name or a shipment date to this cooperation is inventing it.
There is one more gap worth naming, because it will determine whether this story matters in six months. The release describes the cooperation’s initial focus as the industrialization and scalable deployment of INS-2, but it does not describe the platform’s current deployment status anywhere — not in Taiwan, not elsewhere. The underlying architecture was introduced publicly in March 2025, when ficonTEC described a 300 mm double-sided electro-optical wafer tester compatible with existing ATE architectures. What has happened between that introduction and this cooperation — systems deployed, with whom, at what maturity — is not stated in the release, and no update has appeared since. Until ficonTEC or HTSI discloses a deployment, the cooperation should be read as the beginning of an industrialization effort, not as evidence that industrialization has been achieved.
What to watch
The signals that will move this story from cooperation to evidence are specific. First, a customer: a foundry or OSAT naming INS-2 as its CPO wafer-test platform. Second, a deployment: the first INS-2 system delivered or qualified under the cooperation, in a named facility. Third, a manufacturing marker: disclosure that HTSI is building or assembling systems in Taiwan, as opposed to servicing imported ones. Fourth, a performance disclosure: units-per-hour or availability figures from a production environment, ideally from a customer. Fifth, an expansion signal: whether the cooperation extends beyond INS-2 to die-level or module-level test, which ficonTEC flagged as a future direction when it introduced the double-sided architecture.
A competitive signal is also worth watching: if other test-equipment vendors announce their own Taiwan-localized CPO test capacity, the bottleneck thesis is confirmed by imitation; if they do not, and CPO volumes still ramp, the bottleneck was elsewhere.
The fair summary is a narrow one. On October 1, ficonTEC and HTSI agreed to industrialize and deploy ficonTEC’s INS-2 double-sided wafer test platform for CPO manufacturing in Taiwan, combining a 300 mm architecture — electrical probing from above, optical access from below, six-axis alignment, ATE-agnostic by design — with HTSI’s manufacturing, engineering, and service capabilities in Hsinchu. No customer, volume, delivery, or qualification timeline has been disclosed, and no deployment under the cooperation has been announced. That is a modest claim — and precisely because it is modest, it is believable.
Sources and further reading
ficonTEC Service GmbH, “ficonTEC and HTSI Announce Strategic Cooperation to Scale Advanced CPO Test Solutions in Taiwan,” October 1, 2026 — strategic cooperation with Hermes Testing Solutions Inc.; initial focus the industrialization and scalable deployment of the INS-2 double-sided electro-optical wafer-level test platform for advanced silicon photonics wafer testing; 300 mm architecture with electrical probing from the top of the wafer and precision optical access from below; customized slotted wafer chuck, precision wafer positioning, six-axis optical alignment engine, automated wafer handling, vision, probe inspection and cleaning; ATE-agnostic design integrating with industry-standard semiconductor ATE; collaborative engineering framework covering design reviews, local integration, installation, qualification, service, and continuous improvement, with evaluation of units per hour (UPH), equipment availability, and process stability; HTSI’s more than 20 years of semiconductor testing expertise; quotes from Stefano Concezzi, CMO and Corporate Vice President of ficonTEC, and Steven Wang, President of HTSI. No customer, volume, delivery schedule, qualification timeline, or throughput figure is disclosed in the release, and none is asserted here. Aggregator coverage of the announcement appeared on November 3, 2026, a month after the release date; no deployment update under the cooperation has been identified as of publication.
ficonTEC, via optics.org, March 26, 2025 — introduction of the 300 mm double-sided electro-optical wafer tester compatible with existing semiconductor ATE architectures, targeted at AI-driven silicon photonics and CPO demand; background for the INS-2 platform’s architecture. Teradyne and ficonTEC, via PIC Magazine — double-sided silicon photonics wafer probe test cell combining Teradyne’s UltraFLEXplus ATE with ficonTEC’s optical alignment, probing, and wafer-handling technologies, aimed at high-throughput testing of hybrid-bonded PIC/EIC wafers; context for the ATE-agnostic design approach, not a claim about the HTSI cooperation. This article’s account of the Tower–Innolight NPO production milestone (November 3, 2026) and the Marvell–Lumentum agreement (November 2, 2026) is drawn from this publication’s own prior coverage. This article is analysis, not investment advice.