A London chip startup with no product, no customers, and no published benchmarks is worth $3.3 billion. That is the fact to sit with first. Olix — formerly Flux Computing, founded in 2024 by 25-year-old James Dacombe — announced a $312 million Series B on August 3, 2026, at a $3.3 billion post-money valuation, more than tripling its value in the six months since a February round that Data Center Dynamics reported at $220 million and a $1 billion valuation. The round drew Arm, Fundomo, Hudson River Trading, Netflix co-founder Reed Hastings as an angel investor, and the UK government’s Sovereign AI venture fund.
Three months on, the round is worth revisiting not as news but as a thesis statement — because what the money is betting on is unusually specific. Olix is not building a faster general-purpose AI chip. It is building a rack-scale inference system, platform name X-1, in which each stage of inference runs on a specialized chip, the chips hold model weights in on-die SRAM instead of high-bandwidth memory, and the chips talk to each other over light instead of copper. Its first chip, DX-1, is aimed squarely at decode — the stage where a model generates its response, token by token — and the company says it will reach its first customers in the second half of 2027.
The round, and the date that matters
The first thing to get right is the calendar. Coverage of this round has circulated for months — EME Outlook reported it on August 5, Vertex Holdings on August 7, Evertiq on August 12 — and the announcement itself is dated August 3, 2026. Any account presenting the Series B as fresh November news is wrong. What is genuinely worth noting three months later is how the round has aged: no correction, no down-round, no competing announcement has displaced it. That is a thin form of validation, but for a pre-silicon chip company it is the only kind available.
Everything after the funding figure is a company claim. No chip has been taped out in public, no benchmark exists, and no customer has been named. The $312 million is real; the architecture it funds is a promise. This article treats the two accordingly.
The investor list is the most informative part of the announcement, because each name underwrites a different part of the thesis. Fundomo led the round, according to the Financial Times, though Olix itself did not name a lead. Arm’s participation is the strategic signal: the world’s most widely licensed chip architecture company does not write cheques into inference startups casually. Hudson River Trading, a quantitative trading firm, is the latency signal — a firm whose business is measured in microseconds backing a company whose pitch is ultra-low-latency interconnect. Hastings is the founder-operator signal. And the Sovereign AI venture fund’s participation, accompanied by a statement from the UK’s AI Minister Kanishka Narayan — “countries that build chips will build leverage” — is the industrial-policy signal.
The board and executive appointments that arrived with the round reinforce the same reading. Professor Nick McKeown joined the board — a Stanford professor emeritus, co-inventor of software-defined networking, OpenFlow and P4, and winner of the 2025 Marconi Prize. McKeown is the person you recruit when the interconnect is the product. Former Wise chief financial officer Matt Briers, who held that seat for nine years, joined as CFO — the hire you make when the next milestone is manufacturing and supply-chain commitments at scale, not another research result.
Why decode, and why it is a memory problem
To understand what Olix is proposing, split inference into its two phases. Prefill — ingesting the prompt — is compute-heavy and parallel: the arithmetic units are the bottleneck. Decode — generating the response one token at a time — is memory-heavy and serial: for each new token, the model must read its weights, and the arithmetic units spend much of their time waiting for those weights to arrive. In decode, the binding constraint is memory bandwidth, not compute.
That is the opening Olix is aiming at, and it is a real one. A general-purpose GPU carries its weights in high-bandwidth memory — HBM — stacked DRAM sitting on the package next to the processor. HBM is fast for DRAM, at roughly 3.35 terabytes per second on an H100, but it is still DRAM: every token generation means a trip out to the memory stack, and the bandwidth ceiling is set by the memory technology rather than the compute. It is also expensive, supply-constrained, and concentrated in a handful of suppliers — a fact Olix has explicitly leaned on, arguing that forgoing HBM insulates it from the supply constraints facing the rest of the industry.
Olix’s answer is to put the weights in SRAM on the die itself. SRAM is dramatically faster per bit than DRAM, because it stores each bit in a flip-flop circuit that needs no refresh. The cost is density: SRAM takes far more silicon area per bit, so a single chip holds far less of a model. A 100-billion-parameter model at 4-bit precision needs roughly 50 gigabytes of weight storage; no single SRAM chip holds anything like that. Olix’s answer is, in effect, a lot of small trays wired together: distribute the weights across many chips, and make the wiring between them so fast and cheap that the distribution stops mattering.
That is the whole bet. If the interconnect works as claimed, SRAM’s bandwidth advantage becomes a system-level advantage. If it does not — if moving weights between chips costs too much latency, energy, or complexity — then the company has traded HBM’s known bandwidth ceiling for a different, harder problem, and paid for it with silicon area.
The SRAM-for-inference argument is not Olix’s alone. At the Open Compute Project Global Summit in October, d-Matrix demonstrated a hybrid system routing attention layers to H100 GPUs and expert feed-forward layers to its own SRAM-based Corsair XPUs, claiming a halving of time per output token on a 20-billion-parameter model. Those are d-Matrix’s own claims about its own product, and they do not validate Olix — but they establish that the SRAM bandwidth argument is live engineering, not marketing invention.
“Slow and wide”: the interconnect is the chip
Olix calls its interconnect “slow and wide.” Conventional high-speed links chase ever-higher signalling rates per lane. Olix’s claim is the opposite: run many optical lanes in parallel at modest rates, using simple NRZ encoding, and move data directly from die to die at ultra-low latency and low energy cost. The company says 10,000 chips can be connected in a multi-rack scale-up domain, “to run frontier models at an efficiency and speed that are not feasible on traditional systems.”
Two things are worth noticing. The first is that the optics move data; they do not do the math. Olix describes a digital processor performing bit-perfect computation, not an analogue photonic computer. That distinction matters for this desk’s readers: Olix belongs to the optical-interconnect story, not the optical-computing story. The photonics is the nervous system, not the brain.
The second is the scale of the claim. Ten thousand chips in a single scale-up domain is an order of magnitude beyond what today’s copper and co-packaged-optics systems attempt, and it is the claim on which the entire SRAM strategy depends. A 100-billion-parameter model spread across hundreds of chips needs the interconnect to behave as if the chips were one device; a 10-trillion-parameter model — the scale Olix says its architecture reaches — needs thousands. No public evidence exists that the interconnect works at either scale. The company has not disclosed a demonstration, a test chip, or a link-level measurement. “Slow and wide” is, for now, a design philosophy with a funding round attached.
That is not a dismissal. The philosophy is sound engineering: parallel, modest-rate optical lanes are genuinely cheaper in energy per bit than pushing copper or complex modulation to its limits. But a philosophy is not a product, and the gap between the two is where chip startups most often fail: in packaging, in yield, in the unglamorous work of making thousands of optical links behave identically in a hot rack.
There is also a deliberate omission worth naming. Olix says DX-1 needs no HBM, no advanced packaging, and no leading-edge process node. Each “no” is a supply-chain argument as much as a technical one: HBM is scarce, advanced packaging capacity is contested, and leading-edge nodes are booked years out. Designing around all three is a genuine strategic choice — and a constraint. A chip that avoids the leading edge must win on architecture alone, because it cannot win on transistor density.
What the money buys, and what it does not
The $312 million funds three things, according to the company: delivery of DX-1 to first customers in the second half of 2027, build-out of the wider custom silicon platform, and the manufacturing and supply-chain commitments that scaling frontier inference hardware requires. The ordering matters. Manufacturing commitments for a chip that has not yet taped out are the expensive part of this story — foundry slots, packaging, optical component supply, and the working capital to stand behind delivery dates.
It also buys time, and time is the scarcest input here. The second half of 2027 is roughly a year away, and the path between now and then runs through tapeout, bring-up, packaging, board-level debugging, model adaptation, and customer validation — each a stage where optical-interconnect startups have historically slipped.
What the money does not buy is evidence. A $3.3 billion valuation for a company two years old, with no revenue, no named customers, and no benchmark, is a statement about investor appetite for an alternative to the incumbent inference stack, not about the technology. The comparison that matters is with the incumbent: Nvidia’s inference business ships today and benchmarks today, on a cadence Olix must match from a standing start while also solving an interconnect problem Nvidia has spent a decade and billions on.
There is a narrower, more useful way to read the valuation. Multiple outlets described the round as the largest semiconductor venture round ever closed by a European company. Whether or not that superlative survives scrutiny, it captures something real: European deep-tech funding has rarely operated at this scale for a chip company, and the Sovereign AI fund’s participation makes the round a data point about industrial policy as much as about photonics.
What would make this story matter
As with every announcement this desk covers, the right response is a list of checkable developments, not a verdict.
First, tapeout and bring-up: DX-1 returning from the foundry, packaged, and powered on, with the company disclosing the process node, the SRAM capacity per chip, and the interconnect’s measured latency and energy per bit. The “no leading-edge node” claim makes the node disclosure especially informative.
Second, a benchmark on a named model: the company’s claim of more than 10,000 output tokens per second per user on a 100-billion-parameter model, stated with the precision, context length, batch size, and power conditions behind it. Without the conditions it is a headline, not a measurement. A third-party benchmark would be better still.
Third, a customer: a named datacenter operator or inference provider running DX-1 in a real deployment. “First customers in H2 2027” is a deadline the company set for itself.
Fourth, scale-up evidence: a demonstration of the “slow and wide” interconnect across a multi-rack domain at a meaningful fraction of the claimed 10,000 chips, with measured latency and energy across the domain rather than a single link. This is the claim the entire architecture rests on, and a single-link measurement will not settle it.
Until those appear, Olix belongs in a category this desk watches closely but does not celebrate: extraordinarily well funded, strategically backed, architecturally interesting, and entirely unproven. The $312 million is the largest bet yet that inference will be won on memory and movement rather than compute. The next eighteen months will show whether the bet was on the right problem.
Sources and further reading
The round — $312 million Series B at a $3.3 billion post-money valuation, announced August 3, 2026, led by Fundomo according to the Financial Times, with participation from Arm, Hudson River Trading, Reed Hastings, and the UK Sovereign AI venture fund — is reported by Data Center Dynamics, EME Outlook (August 5, 2026), Vertex Holdings (August 7, 2026), and Evertiq (August 12, 2026), and corroborated by Preqin’s company profile. The February 2026 round is reported at $220 million and a $1 billion valuation by Data Center Dynamics; investor Plural has described it as $250 million, and the discrepancy is unresolved in public sources. The DX-1 description, the “slow and wide” interconnect, the 10,000-chip scale-up domain, the SRAM-over-HBM architecture, and the H2 2027 delivery target are company statements reported by Data Center Dynamics and in coverage of Olix’s own announcement; the performance figures — more than 10,000 tokens per second per user on a 100-billion-parameter model, higher throughput per watt, scaling to models of 10 trillion parameters and above — are company claims with no independent benchmark. The d-Matrix figures are d-Matrix’s own claims from its October 2026 Open Compute Project presentation, as reported by Tech Times. Olix’s homepage frames its system as “the token factory for frontier AI.”