On October 20, Japan’s New Energy and Industrial Technology Development Organization (NEDO) selected a joint proposal from Preferred Networks (PFN) and Tenstorrent for a five-year research program to develop an extensible processing unit — an xPU — that integrates AI and CPU chiplets through photonics-electronics integration and advanced packaging. The theme, “xPU Design and Development Incorporating Photonics-Electronics Integration Technology,” sits under NEDO’s post-5G infrastructure initiative for advanced semiconductor manufacturing technology. It is a government-backed bet on a particular answer to the hardest question in AI hardware: how to move data between compute elements without burning the system down.
The announcement, made by the two companies and reported by technode.global on October 22, is notable less for what it promises than for what it combines: a deep-learning chip company with a vertically integrated AI stack, an open-architecture compute company with RISC-V at its core, public research funding over five years, and a bet that photonics — not copper — is the interconnect layer AI hardware needs. No commercialization timetable was disclosed, no performance targets were published, and no funding amount was stated. It is a research award, not a product launch. But the structure of the award tells us something about where governments and the industry think the bottleneck is, and where they are willing to spend to move it.
What the program actually covers
The division of labor is spelled out in the joint announcement. PFN and Tenstorrent will jointly develop system integration technologies for AI processors using photonics-electronics integration and advanced packaging. Beyond that shared task, the work splits along each company’s strengths: PFN will develop AI chiplets with ultra-high memory bandwidth enabled by three-dimensional memory stacking, using leading-edge semiconductor process technologies. Tenstorrent will develop CPU chiplets built on an open architecture, with support for confidential computing.
The target workload is explicit: the companies aim to develop system-level integration of AI processors delivering high performance and high efficiency for both training and inference, directed at what the announcement calls the next wave of AI deployment — agentic AI, physical AI, and scientific AI. After the five-year research program, the companies say they will subsequently work to commercialize the research outcomes for applications including AI agents.
The supporting cast matters. Subcontractors include the University of Tokyo, Kobe University, and Toyo University; the Japan Agency for Marine-Earth Science and Technology (JAMSTEC) and the Japan Atomic Energy Agency (JAEA); and Tenstorrent Japan, which will handle CPU chiplet design and software enabling confidential computing. The presence of marine science and nuclear energy organizations as research partners suggests the program will be evaluated against demanding scientific workloads — simulation, modeling, and data-intensive research applications — not just standard machine-learning benchmarks. That is a serious choice: scientific computing workloads stress memory bandwidth, reliability, and interconnect behavior in ways that conventional AI benchmarks do not.
NEDO lists the project period as up to 60 months. That is a long horizon by AI industry standards — roughly the cadence of two GPU generations — and it is honest about the difficulty of the task: integrating chiplets from multiple teams, demonstrating manufacturability, and building software that can use the hardware efficiently.
Why chiplets and light
The technical logic of the program is the same logic that has driven much of recent AI hardware architecture: the binding constraint is no longer arithmetic, it is data movement.
Modern AI accelerators can perform arithmetic faster than they can fetch the data to operate on. As models grow, an increasing share of system energy and latency goes to moving data — between memory and compute, between chiplets in a package, and between nodes in a cluster — rather than to the computation itself. The von Neumann bottleneck, the memory wall, and the limits of copper interconnect density and power are the same set of problems wearing different clothes. Photonic AI articles in this series have argued this point repeatedly: the physics of moving electrons through copper wires does not scale the way model sizes are scaling.
The xPU program attacks this problem from two directions at once. The chiplet approach decomposes a monolithic processor into specialized dies — AI compute chiplets, CPU chiplets, memory stacks, interface chiplets — that are developed separately and assembled in an advanced package. This lets each component be built on the process technology best suited to it and allows the system to be composed and recomposed for different workloads. The cost of that decomposition is that the interconnect between chiplets becomes the system: bandwidth, latency, and energy per bit at the package level determine what the architecture can do.
That is where photonics enters. Optical links can move data with lower electrical losses over some distances than conventional copper connections, and they are less sensitive to the signal-integrity degradation that plagues high-speed electrical links as data rates rise. Co-packaged optics and photonic interconnect fabrics are one of the few credible answers to the question of how to keep feeding hungry accelerators once copper runs out of headroom. The NEDO program is, at its core, a funded attempt to make that answer real: to develop the integration technology — photonic-electronic co-design, packaging, thermal management, testing — that turns photonics from a laboratory capability into a deployable interconnect layer for AI systems.
Readers of this section will recognize the pattern. Photonic AI accelerators use light for computation itself; this program uses light for the communication between electronic compute elements. Both rest on the same physical bet: that photons move information more efficiently than electrons at the scales AI hardware now demands. The interconnect bet is the more conservative of the two — it does not require optical nonlinearities or all-optical logic, only reliable, manufacturable photonic links integrated with electronics. It is also the bet with the shorter path to a working system, because the compute elements remain electronic and well understood.
The pairing: PFN and Tenstorrent
The choice of partners is deliberate. Preferred Networks is unusual among AI chip companies in that it works across the whole stack: it develops the MN-Core series of AI processors, operates the PFCP cloud platform for AI computing, and builds the PLaMo generative AI foundation model, alongside industry applications. Founded in Tokyo in 2014, PFN has the systems-level experience to connect chiplet design choices to real model and workload requirements — the kind of hardware-software co-design that determines whether an accelerator is useful or merely fast.
Tenstorrent brings the open-architecture play. The company, led by CEO Jim Keller — whose chip-design history spans Apple’s A4/A5, AMD’s Zen, and Tesla’s Full Self-Driving chip — builds RISC-V-based AI processors and licenses its TT-Ascalon RISC-V CPU cores and Tensix AI cores to chip designers including Samsung and LG. The NEDO program’s CPU chiplets are described as built on an open architecture with support for confidential computing: the ability to process data in hardware-isolated enclaves, which matters for workloads where data cannot be exposed to the infrastructure operator.
The open-architecture angle is the geopolitical thread in this story. The NEDO program sits inside a post-5G infrastructure initiative whose premise is domestic technology capability: Japan wants AI computing infrastructure it can build, understand, and modify, rather than depending entirely on tightly integrated proprietary platforms from elsewhere. Open instruction sets and chiplet architectures give system builders more flexibility than closed ecosystems, but they shift responsibility — for interconnects, packaging, compilers, and software compatibility — onto the system builder. This program is, in part, Japan paying to take on that responsibility.
Timing adds context. Tenstorrent closed a $1.5 billion Series E at a $6.2 billion post-money valuation on October 19, 2026 — the day before the NEDO announcement — led by Trace Capital and Innovation X, with participation from Fidelity, T. Rowe Price, ARK Invest, Morgan Stanley, SanDisk, and others, according to Reuters, TechTarget, and the company’s own statement. The round more than doubled the roughly $2.7 billion implied post-money value of its December 2024 financing. The NEDO collaboration is a separate research award; the companies did not link any portion of the financing to it, and the two should be understood as independent events that happened to coincide. Still, the coincidence is instructive: Tenstorrent enters a five-year research program with a newly replenished balance sheet.
What was not announced
The honest reading of this announcement requires dwelling on what it does not say. The companies disclosed no commercialization timetable, no target manufacturing process, no foundry arrangement, no prototype performance figures, and no funding amount. The press release’s claims about “high performance and high efficiency” are aspirations, not measurements — there is nothing to scrutinize yet, and nothing established.
That absence of specifics is normal for a research award at this stage, and it should be read that way rather than as a red flag. But it sets the correct expectations: selection under the program establishes a research framework; it does not guarantee that a resulting processor will reach commercial production, win customers, or outperform incumbents. The development work — integrating components from multiple teams, demonstrating manufacturability, and producing software that can use the hardware efficiently — is the hard part, and it is all ahead of them.
There is also a structural risk worth naming. Five years is a long time in AI hardware. The program targets agentic AI, physical AI, and scientific AI — workloads whose computational character is still evolving. An interconnect and packaging architecture designed now will serve models that do not yet exist. The xPU framing — extensible, composable, built from chiplets — is partly a hedge against that uncertainty: a modular system can be recomposed as workloads change, where a monolithic design cannot. Whether that hedge works in practice depends on the standards and interfaces the program produces, which are the least glamorous and most decisive part of any chiplet effort.
The confidential-computing element deserves a similar level of care. Hardware-enforced confidential computing is a real capability with real value for sensitive workloads, and its inclusion suggests the program takes deployment in regulated and scientific environments seriously. But in a chiplet-based, photonics-integrated system the security boundary must extend across the interconnect fabric, and a photonic link is a new attack surface to reason about. It is early to say anything definitive about that boundary.
The sovereign hardware pattern
Zooming out, the NEDO xPU program is one instance of a pattern that has become impossible to ignore: governments are funding AI hardware development as a matter of national capability, not just industrial policy. Sovereign AI infrastructure — compute that a country or region can build, control, and trust — has moved from a talking point to a line item. The five-year horizon, the post-5G framing, the inclusion of universities and national laboratories, and the open-architecture requirement all point in the same direction: this is about capability and optionality, not about shipping a product next quarter.
For the photonics community, the pattern matters because public money is now flowing specifically to photonics-electronics integration as infrastructure, not just as research. NEDO’s program does not ask whether photonics can compute; it assumes photonics must connect. That is a different and arguably more important question. If light-matter computing is going to matter for AI — and the arguments in this series have been that it might — the interconnect layer is where it will first have to prove itself: reliable, manufacturable, and economically sane at the scale of real systems.
The NEDO program’s modesty is its strength: it does not promise an optical computer, a superintelligence chip, or a revolution. It promises five years of funded engineering on integration, packaging, chiplets, and memory — the unglamorous middle of the stack where systems are actually won or lost. Readers should apply the same standard to every photonic hardware announcement: less attention to the adjective “photonic,” more attention to the nouns — the interfaces, the yields, the software, the workloads.
What to watch
Several milestones will indicate whether this program is on track. First, published technical detail: process nodes, foundry partners, photonic component choices (silicon photonics, co-packaged optics, or something more exotic), and the interconnect standards or interfaces the chiplet ecosystem will use. Second, prototype demonstrations — first of individual chiplets, then of the integrated package — with measured bandwidth, latency, and energy per bit across the photonic fabric, compared transparently against electrical baselines. Third, the software story: compilers, runtimes, and confidential-computing frameworks that can actually program the system. A chiplet architecture without working software is a paperweight with good thermals. Fourth, the scientific workloads: whether JAMSTEC, JAEA, and the university partners publish results on real applications, which would be the strongest evidence that the system works as a computer rather than as a collection of chiplets.
None of those milestones will arrive soon. The honest posture for the next year or two is to track the program’s structure — who is hired, what is published, which subcontractors deliver — rather than expecting hardware. Government-funded semiconductor programs are slow, and slowness is not failure. The question is whether the engineering compounds.
Conclusion
Japan’s NEDO xPU program is a five-year, government-backed attempt to build AI computing infrastructure around the hardest problem in the field: moving data. By pairing Preferred Networks’ AI chiplets and memory-stacking expertise with Tenstorrent’s open-architecture CPUs, linking them through photonics-electronics integration and advanced packaging, and aiming at training and inference for agentic, physical, and scientific AI, the program bets that the future of AI hardware is composable, open, and connected by light.
It is a bet, not a result. No performance figures exist, no product timeline was given, and the engineering is all ahead. But the structure of the bet is informative: sovereign money, public laboratories, universities, an open instruction set, and photonics as the interconnect layer. For readers following AI hardware, the program is worth tracking not because it will displace incumbents tomorrow, but because it is one of the clearest statements yet of where a major industrial economy thinks the bottleneck is — and where it is willing to spend five years trying to move it.
Sources and further reading
This article is based on the joint announcement by Preferred Networks and Tenstorrent dated October 20, 2026 (“PFN and Tenstorrent Selected for NEDO Project on ‘xPU Design and Development Incorporating Photonics Electronics Integration Technology’”), the NEDO notification of selection dated October 20, 2026 under the “Research and Development Project of the Enhanced Infrastructures for Post-5G Information and Communication Systems / Development of manufacturing technologies for advanced semiconductors,” and third-party coverage by technode.global (October 22, 2026). Figures on Tenstorrent’s Series E financing — $1.5 billion at a $6.2 billion post-money valuation, announced October 19, 2026 — are from the company’s statement via ACN Newswire and reporting by Reuters, TechTarget, and Dealroom; the round was led by Trace Capital and Innovation X. Background on Tenstorrent’s RISC-V-based processors and licensing business, and on Jim Keller’s role as CEO, is from the PFN announcement’s company boilerplate. Background on Preferred Networks’ MN-Core processors, PFCP platform, and PLaMo foundation model is from the same release. No performance claims, funding amounts, or commercialization timelines for the xPU program itself were disclosed by the companies or NEDO, and this article asserts none. For the interconnect and memory-bandwidth bottlenecks discussed here, see the earlier articles in this series and reviews of AI hardware in Nature Electronics and Proceedings of the IEEE.